1. Field of the Invention
This invention relates in general to multiplexing protocol handlers to allow access to a shared memory bus, and more particularly, to multiplexing multiple protocol handlers operating in accordance with multiple communication protocols for access to a shared memory bus.
2. Description of Related Art
Today's computing systems have seen several decades of evolution. Evolution has transformed one-of-a-kind, custom built machines into common, everyday appliances found in most homes today. Central processing units (CPU), which were the size of refrigerators, requiring many kilowatts (kW) of power and associated cooling, have been reduced to printed circuit board (FOB) implementations, which have proliferated the computing industry. The relatively few peripherals operated in combination with the early CPUs, including tape readers, teletypes, line printers, etc., were tightly coupled to the early CPUs, thus yielding highly customized computing solutions.
The integrated circuit (IC) is largely, if not wholly, responsible for the drastic reduction in the size and power requirements of the early computing solutions. In addition, the IC is largely responsible for the exponential increase in the computational capabilities of the modern day desktop computer. Through the development of the IC, not only has the CPU been reduced to printed circuit board implementations, but so have peripherals such as Random Access Memory (RAM), high resolution graphics, full motion video drivers and high bandwidth networking cards, to name only a few. Each of the peripheral applications implemented on PCB's share a common communication architecture with the CPU called the computer bus.
The computer bus allows communication between the CPU, or processor, and its peripherals. The computer bus is generally separated into several functional groups such as address, data and control. The address group of the computer bus identifies the specific peripheral attached to the computer bus as well as a particular component contained within the peripheral, such as a register or memory location. The data group of the computer bus defines the information transferred to or received from the peripheral. The control group of the computer bus defines the method or protocol used to effect data or control transfers on the computer bus.
Contemporary computer buses operate in a synchronous fashion, such that all transactions on the computer bus occur synchronously with a rising or failing edge of a master bus clock. The master bus clock, however, is typically slower than the speed of the processor attached to the bus, thereby creating a performance bottleneck at the computer bus level. Subsequently, computer bus speeds have increased in order to reduce the performance bottleneck. However, increasing computer bus speeds requires reduced computer bus lengths in order to control propagation delay. Performance of the computer bus is also limited by the number of peripheral devices attached to the computer bus. The number of peripheral devices attached to the contemporary computer bus increases the effective capacitance of the computer bus, adversely effecting computer bus transfer rates.
One of the earlier computer buses, Industry Standard Architecture (ISA), established itself as an evolutionary enhancement of the time, being well matched to processor performance and peripheral requirements of the early personal computers (PCs). The ISA computer bus, however, soon fell victim to the increasing performance demands of graphical computing. The Video Electronics Standards Association Local (VL) bus provided a subsequent attempt to overcome the limitations of the ISA computer bus architecture. The VL bus strategy is to attach, for example, a video controller, as well as other high bandwidth peripheral devices, directly to the processor's local bus, equating the bus speed of the peripheral device attached to the VL bus to that of the processor's bus speed. The VL bus was successful in increasing the bus speeds of the peripheral devices. However, the VL bus exhibited its own shortcomings, such as a severe limitation on the number of VL bus peripheral devices allowed to operate on the VL bus. In addition, VL bus peripheral devices were necessarily processor dependent.
The Peripheral Component Interconnect (PCI) bus has been developed to provide coherence and standardization, improving upon the ISA and VL bus limitations. The PCI bus specification first appeared in 1992, with subsequent revisions published in 1993, 1995 and 1999. The PCI bus specification provides several features, which potentially allows PCI implementations to accommodate computer architectures for many years to come. PCI bus transfer rates, for example, allow for hundreds of megabytes (MB) of data to be transferred per second. Any peripheral device attached to the PC bus can become a bus master, i.e., responsible for initiating transactions on the PCI bus, thus reducing overhead workload for the processor. The PCI bus is processor independent, such that peripheral devices attached to the PCI bus need only comply with the PCI bus specification to be operable, regardless of the specific processor being used. PCI implementations allow peripheral devices that are newly introduced to the computing architecture to be automatically configured. This automatic configuration process is more commonly referred to as plug and play. The PCI bus, however, along with its ISA and VL bus predecessors, limits the number of peripheral devices that can share a particular PCI bus segment. In order to accommodate multiple PCI peripheral devices and even to accommodate a mixture, for example, of PCI and ISA bus compatible peripheral devices, PCI bridging is used.
PCI bridging allows for expansion of the PCI bus, such that multiple PCI peripheral devices can operate on the PCI bus. These are separated into their own PCI bus segments and then bridged to allow access to the PCI bus. Several types of bridges exist, for example, such as the PCI-to-PCI, Host-to-PCI and PCI-to-legacy bus bridges. The PCI-to-PCI bridge allows multiple PCI bus segments to be interconnected, such that each segment allows a fixed number of PCI peripheral devices to be connected to the PCI bus.
The advent of the PCI bus has allowed a multitude of computing peripherals to be integrated with a single host server or a multitude of host servers. Storage devices, for example, are becoming an increasingly prevalent peripheral as electronic storage needs are increasing to maintain pace with today's computing society.
Storage Area Networks (SAN) are networks that connect the storage devices or systems to their hosting servers. SANs are differentiated from previous interconnection schemes in that the SANs allow centralized management of one large storage area, while facilitating connectivity between the host servers and the storage devices. Historically in SAN environments, physical interfaces to storage devices consisted of parallel Small Computer Systems Interface (SCSI) channels supporting a small number of SCSI devices. More recent developments of SANs, however, have begun to use new technologies to connect greater numbers of host servers and storage devices.
Enterprise System Connection (ESCON®), for example, was a first attempt at creating a SAN environment that allowed growth in the numbers of host servers and storage devices existing within the SAN by integrating the use of fibre optic technology. The ESCON® model, however, generally limits the interconnection to only ESCON® compliant hosts and ESCON®, compliant devices. Fibre Connectivity (FICON), which is based on the industry standard Fibre Channel architecture, is one of the newest fibre optic channel standards being employed today.
Although ESCON® is a relatively mature technology, large numbers of communication subsystems, printers, tape drives, storage subsystems, etc. continue to be produced which support the ESCON® protocol. With the large numbers of ESCON® peripherals available to interface with the PCI based host systems, along with the emerging FICON technology, as well as the large number of SCSI legacy peripherals, an interconnect device is needed that would have the capability to mix and/or match the various protocol handlers on a single card. The interconnect device should also have multiplexing capability to facilitate management of multiple control and data streams into a single control path and a single data path.
Prior art PCB solutions have either utilized large, non-PCI compliant PCBs that require unique power and packaging costs, or have chosen to package only one or two protocol handlers on a PCI compliant PCB, which limits the data handling capacity of the PCI compliant PCB.
It can be seen, therefore, that there is a need for a method and apparatus that provides bus access to a plurality of protocol handlers, while multiplexing and arbitrating the bus access as required.
Furthermore, there is a need to place the protocol handlers and protocol multiplexers on a single circuit to significantly reduce the space required for such functions.
It can further be seen that there is a need for a method and apparatus allowing a mixture of protocol handlers on a single circuit, so that interconnect access can be gained by ESCON®, FICON, SCSI, etc. based interface protocols without requiring the need to bridge each protocol used.